Bohemia, New York — Data Device Corporation (DDC) has introduced their Enhanced Miniature Advanced Communication (Mini-ACE®) terminals which serve as interfaces between a host processor and a MIL-STD-1553 bus. The Enhanced Mini-ACE series is DDCs fifth generation of integrated data bus terminals following AIM-HY, AIM-HYer, ACE, and Mini-ACE Plus.
Backwards compatible with DDCs Mini-ACE and Mini-ACE Plus for legacy applications, the enhanced model offers additional functionality in many areas. Enhanced Mini-ACE configurations include RT only and BC/RT/MT versions with 4K words of internal RAM, 64K word internal RAM with RAM parity checking. Enhanced Mini-ACE units are packaged in one square inch ceramic flatpaks providing compatibility with the Mini-ACE. The enhanced units are available with a choice of 5V or 3.3V internal logic, and 5V transceivers with options for 1553, McAir, or MIL-STD-1760 compatibility.
The Enhanced Mini-ACE's BC architecture includes an internal message sequence control processor, a general purpose queue, and user definable interrupts. The internal processors 20 instruction set includes conditional operations based on results of messages or user defined flags, along with jumps, subroutine calls, and timing control. This enables a highly autonomous capability for operations such as minor and major frame generation, asynchronous message transmission, flexibility in data buffering, and message retry and bus switching strategies. The flag bits, general purpose queue, and user definable interrupts program a high degree of flexibility in reporting message status, timing, and data information from the BC to the host processor.
The RT architecture provides multiprotocol flexibility for MIL-STD-1553 (Notice 2), STANAG 3838, and McAir, as well as a wide choice of memory management options. These include subaddress single buffering, double buffering for individual receive subaddresses, circular buffering for individual subaddresses, and an option for global circular buffering for multiple (or all) subaddresses. The selective MT monitor mode provides message filtering based on RT address, T/R bit, and subaddress. The RT and selective monitor, which can work concurrently, can provide interrupts at 50% and 100% rollover which enable the RT/monitor and the host to alternately access different multimessage areas of shared RAM.
Like the ACE and Mini-ACE, the Enhanced Mini-ACE supports a variety of host interface configurations. These include shared RAM and DMA configurations; direct connections to 8, 16, and 32-bit processors; support of multiplexed or non multiplexed address/data buses; and interfaces to either microprocessor memory buses or microcontroller I/O ports, without external buffers and with a minimum of glue logic. In comparison to the ACE/Mini-ACE, the Enhanced Mini-ACE reduces the hosts maximum hold off time for a shared RAM host interface, and increases the maximum request to grant time for a DMA interface. The interrupt request output may be configured to provide a choice of a pulse or level type signal.
The Enhanced Mini-ACE can operate from a choice of 10, 12, 16, or 20 MHz clock inputs. A comprehensive built in self test includes fully autonomous verification of the encoder/decoder, registers, transmitter watch dog timer, and protocol. There is a separate built in self test for exercising the 4K or 64K internal RAM. Other features include a large set of interrupt conditions, an interrupt status queue for RT and MT modes with filtering based on valid and/or invalid messages, multiple options for time tagging, and an RT auto boot feature which allows the Enhanced Mini-ACE to initialize as an on line RT with the busy bit set following power turn on.
Data Device Corporation is an international leader in high-reliability data conversion interface components and subsystems for military and commercial applications. Established in 1964 with the introduction of the first synchro-to-digital module, DDC's design and manufacturing facility is located in Bohemia, New York.