Rad Hard/Space Components

SP’ACE

Q. What are the BU-61582’s (SP’ACE’s) radiation characteristics?

A.

• Total Dose: 1 Mrad
• Single Event Upset: 10^-7 errors per bit-day (LET threshold of 59 Mev/mg/cm²)
• Single Event Latchup: Immune
• Dose Rate: 10¹⁰ rads(Si)/sec
• Neutron Fluence: 2•10¹³ neutrons/cm²

Q. What is the ESD rating of the BU-61582 SP’ACE?

A. The ESD rating of the BU-61582's digital I/O signals is Class 1. That is, it is between 0 and 1500 volts. The MIL-STD-1553 analog transceiver signals (TX/RX-A, TX/RX-A*, TX/RX-B, and TX/RX-B*) provide an ESD immunity level of 7,000 volts with no protection. This value may be increased by means of external circuitry, involving the use full-wave diode bridges, and either Zener diodes or transorbs.

Q. Does the SP’ACE support a software-programmable RT address?

A. There are two different versions of the SP’ACE: (1) the BU-61582XX, for which the RT address is hardwired; and (2) the BU-61583XX, for which the RT address may be programmed by means of software control. To make the BU-61583's RT address software programmable, you would need to connect RTAD4-RTAD0 to D5-D1, and RTADP to D0.

Q. For SP’ACE, what are the advantages of a shared RAM interface over the use of dual Port RAM?

A.

1. Dual port RAM is significantly more expensive than conventional single-port RAM. It also uses up more real estate than using the shared RAM that's inside the SP’ACE.
   
   
2. If dual port RAM is used, the design will still need external tri-state buffers for the address and data buses, to isolate the SP’ACE buses from the buses connecting to the host processor. These are necessary to enable the host to access the SP’ACE’s internal registers. This entails additional real estate and cost.
   
   
3. In terms of software, there are no differences between the use of internal share RAM and external dual port RAM.
   
   
4. The penalty, in terms of bus bandwidth utilization for using shared, rather than dual port RAM is very insignificant. It's a function of the level of bus traffic, but even assuming 1,000 32-word messages per second, and assuming the use of 8-bit RAM in a SP'ACE, a host bus contention situation will only occur about 2.0 to 2.5% of the time.
   
   
5. There is no difference, in terms of worst-case holdoff time between the use of dual port RAM and shared RAM. The reason is that even with external dual port RAM, there will still be a need to access the SP’ACE's registers (through the tri-state buffers). For a dual port RAM interface, the SP’ACE’s host interface will need to be configured for its transparent mode. This results in a one clock cycle increase over the buffered (shared RAM) configuration in the time required to access the SP’ACE’s internal registers.

Q. Does the SP’ACE include a mechanism to ensure against the possibility of a “babbling terminal”?

A. In compliance with MIL-STD-1553B, the SP'ACE and all of our other 1553 products include a transmitter timeout circuit. That is, they include a circuit that operates independently from the encoder/transmitter to automatically shut down the transmitter if it attempts to transmit longer than the longest allowable transmission time of 660 µs. For the SP'ACE, the timeout value is 668 µs. If the transmitter timer (sometimes called a watchdog timer) times out, it will: (1) shut down the Manchester encoder circuit; and (2) bring the TX_INH (transmit inhibit) inputs to the CH. A or CH. B transmitter to logic "1", which shuts down the 1553 transmitter.

Q. We have an application for the BU-61582 SP’ACE, involving both RT and Monitor modes. When the SP’ACE is in Monitor mode, we need very high assurance that the SP’ACE will never attempt to transmit on the 1553 bus. What do you suggest?

A. The recommended configuration is for us to supply you with a version of the BU-61582 SP'ACE product that is modified to bring out the TX_INH (Transmit Inhibit) signals. The SP'ACE's mode (BC, RT, Monitor, or simultaneous RT/Monitor) is selectable, by host software, by means of Configuration Register #1. Keep in mind that the SP'ACE is designed to never transmit while in Monitor mode. To provide an extra level of assurance that the SP'ACE will never transmit on the bus while in Monitor mode, I would recommend bringing out the TX_INH signals. This way, the SP'ACE monitor is prevented from transmitting by two independent methods: (1) under non-fault conditions, the SP'ACE's Monitor mode will never attempt to transmit on the 1553 bus; and (2) if there was a fault in which the monitor did attempt to transmit on the 1553 bus, the assertion of the respective TX_INH input to logic "1" by external hardware will serve to block any transmission on the 1553 bus.

Q. Is there a Standard Military (DESC) drawing for the BU-65621 JRAD chip?

A. Yes. The number is 5962-94A03. In addition, there is also an Altered Item Drawing (AID)from Honeywell SSEC, who is the foundry for the BU-65621 chip. Honeywell's number for the AID is 22019712.

Q. Does the BU-65621 include any internal memory?

A. The BU-65621 chip does not include any on-chip memory. However, we can also
supply a transceiverless version of the BU-61582 SP'ACE, the BU-61582X0. The BU-61582X0 hybrid includes the JRAD protocol chip that's in the BU-65621, plus 16K X 16 of internal RAM, but no transceiver.

Q.Can the BU-65621 operate as a BC, RT or MT?

A. In addition to self-test mode, the BU-65621 has five (5) normal modes of operation:

1. Bus Controller (BC)
2. Remote Terminal (RT)
3. Word Monitor
4. Selective Message Monitor
5. Simultaneous RT and Selective Message Monitor

Q. We plan on using Honeywell's 32K by 8-memory chip in conjunction with the BU-65621. We are trying to decide whether to use one or two memory chips for the BU-65621’s external, buffered RAM interface. How does the memory width effect the data throughput of the 1553 controller?

A. Honeywell's 32K X 8 RAM will work. We integrate this chip into our SP'ACE hybrid, which also includes the same "JRAD" chip that's in the BU-65621. The use of 8-bit RAM should not have any appreciable effect on throughput.

However, you should be aware that the time for your host processor to access the buffered RAM (through the BU-65621) increases by roughly a factor of two (with respect to using 16-bit wide RAM), due to the increased time to transfer data to/from the 8-bit RAM. That is, assuming a 16 MHz clock input, an increase from 312 ns max to 562 ns max for an uncontended access, and an increase from about 3.0 us to about 6.0 us for a contended access.

If you’re considering the use of the BU-65621 with the Honeywell RAM chip, note that the BU-61582X0 transceiverless SP’ACE integrates these two chips into a single 1.0 by 1.9 inch hybrid.