Q. What are the pinout differences between Mini-ACE™ and Enhanced Mini-ACE™?

A. The Mini-ACE™ and Enhanced Mini-ACE™ have nearly identical pinouts,with the following exceptions:

Pin 25:For Mini-ACE™, this signal is "Test Output (RX-B)". For Enhanced Mini-ACE™, this signal is INCMD_L/MCRESET_L (output).

Pin 26:For Mini-ACE™, this signal is "Test Output (RX-B*)". For versions of the Enhanced Mini-ACE™ with 64K X 16 RAM (BU-61864/61865), this signal is "Vcc-RAM" (+5V). For the versions of Enhanced Mini-ACE™ with 4K X 16 RAM, this pin is UPADDREN (see below).

Pin 37:For both Mini-ACE™ and Enhanced Mini-ACE™, this signal is "VCC-LOGIC". However, for the BU-61743, BU-61843, and BU-61864 versions of the Enhanced Mini-ACE™, this voltage is +3.3V. For the BU-61745, BU-61845, and BU-61865 versions of Enhanced Mini-ACE™, this voltage is +5V.

Pin 65:For Mini-ACE™, this signal is "Test Output (RX-A*)". For Enhanced Mini-ACE™, this signal is LOGIC GND.

Pin 67:For Mini-ACE™, this signal is "Test Output (RX-A)". For Enhanced Mini-ACE™, this signal is LOGIC GND.
In addition, for versions of Enhanced Mini-ACE™ with 4K of RAM (BU-61843(5) BC/RT/MT and BU-61743(5) RT), note that there are different, and potentially different pin functions on the following pins:

Pin 26:UPADDREN. If this pin is logic "1", then pins 8 (A14), 66 (A15), 70 (A12), and 71 (A13) function as the upper 4 address lines, A15-A12. Note that this provides compatibility with the BU-65178 and BU-61588 Mini-ACE™, and the BU-61688/61689 Mini-ACE™ Plus.
However, if UPADDREN (pin 26) is connected to logic "0", then the functions of these four pins behave more like the BU-65179 version of the Mini-ACE™, as follows:

Pin 8:CLK_SEL_0

Pin 66:CLK_SEL_1
CLK_SEL1 and CLK_SEL_0 are used to designate the frequency of the CLK_IN input as follows:
CLK_SEL_1 CLK_SEL_0 Clock Frequency
0 0 10 MHz
0 1 20 MHz
1 0 12 MHz
1 1 16 MHz
Note that for all versions of Enhanced Mini-ACE™, clock frequency selection may also be done via software.

Pin 70: RT_AUTO_BOOT* If this pin is connected to logic "0", the Enhanced Mini-ACE™ will initialize in RT mode with the Busy bit set following power turn-on. If hardwired to logic "1", the Enhanced Mini-ACE™ will initialize in either Idle mode (if it's an RT-only part), or as in BC mode (if it's a BC/RT/MT part).

Pin 71:Assuming that UPADDREN is logic "0", then this pin must be tied to Vcc-LOGIC (+5V or +3.3V).

Q. For RT operation, what are the functional and architectural differences between the Mini-ACE™ and the Enhanced Mini-ACE™?

A. The Enhanced Mini-ACE™ is available with versions for which the logic sections may be powered by 3.3V. The Mini-ACE™ is not; its logic may only be powered by +5V. In addition, the Enhanced Mini-ACE™’s ENHANCED CPU ACCESS feature allows for a shorter maximum holdoff time for processor-to-ACE memory and register transfers. This time has been reduced from about 2.8 µs max (at 16 MHz) for Mini-ACE™, to about 600 ns max (at 16 MHz) for Enhanced Mini-ACE™.
Also, for RT mode, the Enhanced Mini-ACE™ includes the following new architectural features:

(1) Global circular buffer. That is, a circular buffer that may be used by all subaddresses or a subset of all subaddresses. Note that both the Mini-ACE™ and Enhanced Mini-ACE™ RTs have circular buffers that may be programmable by individual subaddresses.

(2) The addition of a 50% rollover interrupt for circular buffers. Note that both the Mini-ACE™ and Enhanced Mini-ACE™ also have interrupts for (100%) circular buffer rollover.

(3) An interrupt status queue. This provides a chronology of up to the last 32 interrupts, including the reason(s) for the interrupts, and pointers to the individual message descriptors.

(4) Fully autonomous built-in protocol and RAM self-tests. For the Mini-ACE™, a protocol self-test may be done by means of the host processor writing and reading/verifying test vectors.

(5) With the Enhanced Mini-ACE™, there is a bit more flexibility for implementing a
software programmable RT address. That is, with Mini-ACE™, to do this, RTAD4-0 and RTADPmustbe connected to D5-D0. This means you can't select between an address from an external connector or software by means of software. With the Enhanced Mini-ACE™ RT, you can do this fully under software control.

Q. Is a software driver developed for the Mini-ACE™ compatible with the Enhanced Mini-ACE™?

A. The Enhanced Mini-ACE™ is software backfit compatible with the Mini-ACE™, with the following two exceptions:

(1) In the BU-61588, bit 8 of the RT BIT Word Register (and in the BIT word transmitted to the BC) is CHANNEL B/A*. With the BU-61865, bit 8 is BIT TEST FAIL. It will set to a value of logic “1” if there is a failure of the Enhanced Mini-ACE™’s built-in protocol self-test.

(2) With the Mini-ACE™, to run the protocol self-test, it is necessary for the host processor to write and read/verify the test vectors. With the BU-61865 Enhanced Mini-ACE™, all the host processor needs to do is to write a register bit; the self-test vectors are then run autonomously by the BU-61865 Enhanced Mini-ACE™. When the self-test is complete, an interrupt request will be issued to the host (if enabled), and the results of the self-test will be available in registers to be read. In addition, the Enhanced Mini-ACE™ provides a separate additional autonomous self-test for the 4K or 64K internal RAM. Alternatively, there are self-test vectors for the Enhanced Mini-ACE™ that may be run from the host processor. Note however that these test vectors are different than those for the Mini-ACE™.

Enhanced Mini-ACE™: Logic Compatibility

Q. Is the 3.3 volt Enhanced Mini-ACE™ 5 volt tolerant?

A. Yes.The 3.3V Enhanced Mini-ACE™ is 5 volt tolerant. The absolute maximum rating for “Logic Input Voltage” is 6.0V. The Enhanced Mini-ACE™’s input and I/O pad cells include clamping diodes to LOGIC GROUND, but do not include clamping diodes to V_CC.

Q. Are there internal pull-up resistors on the Enhanced Mini-ACE™’s digital inputs?

A. Yes. There are pull-up resistors on all of the inputs and I/O, except for the clock input. More accurately, these are current sources from V_CC, with the current value in the range from 50 to 350 µA. In addition, there are Schmidt triggers on all digital input signals (including I/Os), including the clock input.

CLK_IN is a CMOS type input. Its V_Ilis 0.2•V_CCmax, its V_IHis 0.8•V_CCmin, and the minimum Schmidt hysterisis window is 1 volt. The other inputs are TTL type, with V_Il= 0.7V max, V_IH= 2.1V min, and a minimum Schmidt hysterisis window of 0.4V.

Enhanced Mini-ACE™: BC Mode

Q. For the Enhanced Mini-ACE™, are there any "rollover" enforcement for the op-code instruction list? Same question for the Command/Status blocks.

A. There are no rollover enforcements for the Enhanced Mini-ACE™’s BC op code instruction list or for the Command/Status blocks.

Q. For the Enhanced Mini-ACE™, what is the minimum BC inter-message gap time?

A. For the Non-Enhanced BC mode (i.e., not using the autonomous BC message sequence control engine), the nominal BC intermessage gap time for the Enhanced Mini-ACE™ is the same as for the Mini-ACE™ (Plus) hybrids, approximately 9.5 µs.

However, for the Enhanced Mini-ACE™’s enhanced BC mode (using the autonomous message sequence control engine), the typical value for intermessage gap time is approximately 10 clock cycles longer than for the non-enhanced BC mode. This accounts for the time for the message sequence control engine to fetch op code and parameter words from the BC Instruction List, and to execute the op code (assuming an Execute Message (XEQ) instruction). That is, an additional 1.0 µs at 10 MHz, 833 ns at 12 MHz, 625 ns at 16 MHz, or 500 ns at 20 MHz.

Also, note that if ENHANCED CPU ACCESS, bit 14 of Configuration Register #6, is set to logic “1”, the Enhanced Mini-ACE™’s arbitration logic will interleave host transfers in between individual SOM or EOM word transfers. In this scenario, host transfers could have the effect of lengthening the intermessage gap time.

For each host access during an SOM or EOM sequence, the intermessage gap time will be lengthened by 6 clock cycles for each host access in buffered mode, or by 7 clock cycles in transparent mode. Since there are 7 internal transfers during SOM and 5 during EOM, this could theoretically lengthen the intermessage gap (for buffered mode) by up to 72 clock cycles; i.e., up to 7.2 µs with a 10 MHz clock, 6.0 µs with a 12 MHz clock, 4.5 µs with a 16 MHz clock, or 3.6 µs at MHz clock. Note that this worst case delay would only occur in the case of a burst access by the host processor.

However, note that if you set ENHANCED CPU ACCESS to logic "0", the maximumhostwait time (i.e., maximum delay from the STRBD*/SELECT* inputs asserted low-to-READYD* output low) increases from 612 ns (for a host read) or 550 ns (for a host write) to about 2.8 µs. Therefore, the tradeoff is between increased host holdoff time (which, on average, won't occur very often) vs a potential occasional increase in the BC intermessage gap time.

Q. Does the call stack "clear" when a Halt instruction is executed?

A. The call stack pointer clears when you start the bus controller, by means of the Start/Reset Register.

Q. Does the BC General Purpose Queue pointer point to the next location in the queue? That is, in order to see the last value placed into the queue, should I examine the previous location (modulo 64)?

A. The general purpose queue pointer points to the next address location, modulo 64. That is, the location following the last location written by the BC.

Q. When using the Enhanced Mini-ACE™ Enhanced BC mode, is it safe to use locations 0x100 - 0x107 for messages, etc. Or should they still be “RESERVED”?

A. Yes, it is safe to use these locations for control/status blocks or data blocks. In the Enhanced BC mode, these locations are not “reserved”.

Q. What is the number of words in the BC Control/Status block?

A. The value of the pointer parameter in the BC instruction list (e.g., for the Execute Message instruction) must be modulo 8. That is, the three LSBs of this word must always be “000”. The length of the Control/Status block should be:
8 words – for messages that are not RT-to-RT transfers and are not referenced by an XQF (Execute and Flip) instruction, or
16 words – for messages that are either RT-to-RT transfers and/or are referenced by an XQF (execute and flip) instruction.

Q. Does the op code parity bit cover just the op-code field, or the entire instruction word? What happens in the case of a parity error?

A. The parity bit covers the entire instruction code word, not just the op-code field. Note that the parity is odd. If the BC fetches an instruction with a parity error, an erroneous op code and/or one of the “fixed value” bits (bits 9-5) is the wrong value, then the BC will trap out (halt), and the BC OP CODE PARITY ERROR interrupt will be issued, if enabled.

Q. If a masked status bit is set in an RT status response for the most recent message, will this cause the "BAD MESSAGE" condition code to be set?

A. No.

Enhanced Mini-ACE™: RT Mode

Q. How does the Enhanced Mini-ACE™’s RT global circular buffer option operate?

A. The RT Global Circular Buffer is a programmable option for any subset of the 30 receive(/broadcast) and/or 30 broadcast subaddresses. The size of the global circular buffer is programmable by means of bits 11, 10, and 9 of Configuration Register #6.

To enable received words for a particular receive(/broadcast) subaddress to be stored to the global circular buffer, it is necessary to program bits 15, 7, 6, and 5 of the respective subaddress control word to values of logic "1".

If SEPARATE BROADCAST DATA is enabled (bit 0 of Configuration Register #2 = logic "1"), then to enable received words for a particular broadcast subaddress to be stored to the global circular buffer, it is necessary to program bits 15, 2, 1, and 0 of the respective subaddress control word to logic "1".

The pointer to the RT circular buffer is stored in location 101 (if area A is the currently active area, per CURRENT AREA B/A*, bit 13 of Configuration Register #1) or 105 (if area B is the currently active area).

Enhanced Mini-ACE™: Self-test

Q. What are the Enhanced Mini-ACE™’s self-test capabilities?

A. In Bus Controller and Remote Terminal modes, there is a continuous on-line loopback self-test performed for each message transmitted. In the loopback self-test, the respective (A or B) receiver/decoder samples each word transmitted. For all words transmitted by the Enhanced Mini-ACE™ (or for that matter, ACE or Mini-ACE™) BC or RT, the validity of the "received" version is verified. Also, there is a bit-by-bit comparison check between the transmitted and received versions of the last word transmitted.

If there is a failure of the loopback self-test, the "ERROR FLAG" and "LOOP TEST FAIL" bits will be set in the message's Block Status Word. In addition, if enabled, an interrupt will be issued to the host processor. Also, in RT mode, bit 14 (for Channel B) or bit 13 (for Channel A) will be set in the RT BIT Word Register, and transmitted to the BC in response to a Transmit BIT word mode command. In addition, in RT mode, assuming that bit 2 of Configuration Register #3, RTFAIL/RTFLAG WRAP ENABLE, is programmed to logic "1", the Terminal Flag bit will be set in the status word response to the next non-broadcast message.

As for the comprehensive protocol self-test and RAM self-test, these may be initiated by a command from the host processor at any time, by writing logic “1” to the respective bit of the Start/Reset Register. The results of these tests may are then made available to the host by means of polling and/or interrupts. If the protocol self-test fails, bit 8 (BIT TEST FAIL) of the RT’s BIT word and BIT Word Register will be set to logic “1”. However, keep in mind that when either the protocol or RAM self-test is being performed, the Enhanced Mini-ACE™ will be offline; that is, not able to receive or transmit on the 1553 bus.

Q. Are the Enhanced Mini-ACE™ internal registers corrupted as a result of running the self-test vectors?

A. No. When the self-test is performed, the first part of the test stores the value of the registers temporarily into memory. When the test is complete, the register values are restored. As long as the host does not attempt a write operation before the test is complete, the final values in the registers will be the same as the initial values.

Note that the Time Tag Register will continue to increment at the same rate as prior to the start of the test (i.e., no time is lost). Also, the protocol self-test cannot be performed if the BC or Monitor is presently enabled (started), or the RT is not idle, or the memory test is currently in progress. The BC frame timer and message timers will be restored to zero, but this should not matter since these will be reinitialized when the BC is enabled.

Also, if the protocol self-test fails and assuming that RTFAIL-TO-TERMINAL FLAG AUTO-WRAP is enabled, the Terminal flag status bit will be set to logic “1” and the results of the RT’s last transmission loopback test will be lost. The command stack register, data address pointer register, and the Sub address Control Word Register will be reset to zero. In addition, the interrupt output will be cleared; it will re-asserted only if the BIT test complete interrupt was enabled.

Q. For the Enhanced Mini-ACE™ built-in self-test, if the flag supplying the results of the comprehensive protocol self-test and RAM self-test is faulted in the “PASS” state, how is that detected?

A. While the Enhanced Mini-ACE™’s protocol or RAM self-test is being performed, the host may access the BIT Test Status Register (register address 1Ch). However, the host may not access any of the other registers; if it does, the self-test will be aborted.

While the test is being performed, the "PROTOCOL SELF-TEST PASSED" bit (bit 12) and "RAM BUILT-IN SELF-TEST PASSED" bit (bit 5) will normally be logic "0". If you poll this register while the self-test is being performed and the "PASSED" bit for the test that's being performed returns a value of logic "1", this indicates that the bit is stuck high.

Also, after the self-test completes, you may poll the final value of the self-test ROM address register and self-test data register. These are both test registers, which are made accessible by setting 64-WORD REGISTER SPACE, bit 2 of Configuration Register #6, to a value of logic "1".

Assuming that the test has run to successful completion, the expected values of these two registers are known. If one of the "PASSED" bit is logic "1", but the value of either of these registers doesn't match the expected value, this would indicate a fault in the self-test logic.

Q. How is the Enhanced Mini-ACE™’s self-test initiated?

A. For Enhanced Mini-ACE™, the protocol and RAM self-tests may be initiated by means of the Start/Reset Register (write only, register address 03). In particular, to initiate the RAM self-test, you would write a value of logic "1" to bit 9 of this register. To initiate the protocol self-test, you would write a value of logic "1" to bit 7.

Q. What exactly is done in the Enhanced Mini-ACE™ RAM self-test?

A. The RAM test works as follows: a pattern of 0, 1, 2, 3,... is written to addresses 0, 1, 2, 3..., (data = address) and then read back and verified. After that, the inverse pattern ("data = address inverted") pattern is written, read back, and verified.

Q. How long does the Enhanced Mini-ACE™’s RAM self-test take to perform?

A. The memory test takes a total of 10 clock cycles per RAM location. That is, for each word location, it takes 5 clocks to write and read/verify the "data = address" pattern, and another 5 clocks to write and read/verify the "data = inverted address" pattern.

Therefore, for an Enhanced Mini-ACE™ hybrid with 4K RAM locations, it takes a total of 40,960 clock cycles to perform the memory self-test. For a clock frequency of 16 MHz, this is 2.56 ms. For a hybrid with 64K RAM locations, it takes a total of 655,360 clock cycles to run the memory self-test. For a clock frequency of 16 MHz, this is 40.96 ms.

PCI Enhanced Mini-ACE™

Q. Is the BU-62864 PCI Enhanced Mini-ACE™ PCI 3.3 or 5.0 compliant?

A. It's logic is 3.3 volt powered, and intended for use only in a 3.3 volt PCI signaling environment.

Q. Is a self-test performed on the PCI Enhanced Mini-ACE™ in the same manner as for the Enhanced Mini-ACE™ ?

A. No. However, you will still be able to run essentially the same self-test for the "1553" portion of the terminal that is performed on the BU-61865 (Enhanced Mini-ACE™). Note however that the stimulus/response vectors will need to be written and read/verified by the PCI host; that is, the vectors are not included in on-chip ROM.

Q. Does the PCI Enhanced Mini-ACE™ include RAM parity checking?

A. Yes. The BU-62865, the 64K RAM version of the PCI Enhanced Mini-ACE™, does incorporate RAM parity checking.