A. In most cases system designers should use the 8-bit address value even if they are using a 16-bit processor and the DD-42900 is connected for 16-bit mode. In some rare cases, 16-bit processors which don’t use byte addressing can be connected to the DD-42900 by grounding the A0 input on the DD-42900 and connecting A0 on the processor to A1 on the DD-42900. It is only for these cases where the address bus between the host and the DD-42900 is shifted by one bit that the address (relative to the processor) is listed as the 16-bit address in the data sheet. Connecting the processor this way helps save memory mapped address space for the system designer. (Note: DD-42900 Users Manuals published after October 1997 will no longer contain references to “16-bit addresses.”)

A. The INT/MOT* input signal should be left unconnected (or tied to a logic 1) for an Intel mode interface and grounded for a Motorola mode interface. The INT/MOT* signal merely provides some front end signal gating for the READ* and WRITE* signals generated internally to the DD-42900. When in Intel mode, these signals are developed directly from the READ* and WRITE* input pins. When in Motorola mode, these signals are developed from the RD/WR* and DS* (Data Strobe) input signals. The INT/MOT* input does not have any effect on the byte or word ordering of multi-byte and multi-word transfers. The address polarity inputs (POL SEL A0 and POL SEL A1) are used to control the byte and word transfer order (big endian and little endian modes).

A. Each of the POL SEL input signals should either be left unconnected (these signals are pulled up internally) or grounded. The POL SEL signals only effect 16- and 32-bit transfers to and from the DD-42900. They do not affect the addressing of 8-bit control or status registers. The POL SEL A0 is only used when the DD-42900 is operated in 8-bit mode. When the DD-42900 is operated in 16-bit mode, the POL SEL A0 must be connected to ground.

The POL SEL A0 controls the order in which the high and low order bytes of a (16-bit) word are written to and read from the DD-42900. When POL SEL A0 is a logic one then the high order byte of a word is written in address X and the low order byte is written in address X+1. This is the scheme typically employed by Motorola processors. When POL SEL A0 is a logic zero then the low order byte of a word is written in address X and the high order byte is written in address X+1. This is the scheme typically employed by Intel processors.

The POL SEL A1 controls the order in which the high and low order words of a 32-bit word are written to and read from the DD-42900. When POL SEL A1 is a logic one then the high order word of a 32-bit word is written in address X and the low order word is written in address X+2. When POL SEL A1 is a logic zero then the low order word of a 32-bit word is written in address X and the high order word is written in address X+2.

A. The Data Match table “skips” every other word to maintain a constant offset for each corresponding Data RAM location. Each Data RAM location is a full 32-bits wide. The address of the Data RAM location is always 200 (hexadecimal) less than its corresponding Data Match Table entry. Because of this mapping, when writing to address 200h, the same 16-bit data will appear at both 200h and 202h. The effect of this mapping is that between the addresses of 200h to 3FFh the A1 bit of the address bus, which is internal to the DD-42900, is not used.

A. The DD-42900 can enter a Master Reset State either via hardware, by momentarily asserting the MASTER RESET* input signal or via software, by writing a logic 1 into the LSB of the Master Control Register. Once in a Master Reset State, the DD-42900 is automatically “off-line” and will not respond to any software or hardware functions until taken out of the master reset state by writing a logic zero to the LSB of the Master Control Register. It is especially important to take the DD-42900 out of the Master Reset State before attempting to read any data from the DD-42900 on systems that have either the DTACK* or READY signals connected to the host processor. A good way to tell if the DD-42900 is out of reset mode is to look at the 1Mhz ARINC CLK output. If this clock is running then the DD-42900 is not in the reset state.

A. Yes. The interrupt outputs on the DD-42900 provide additional capability to systems which have interrupts available. Connecting the interrupt outputs to the host processor is optional. The interrupt features can be used to help quickly detect new receive data; FIFO full or empty conditions or an error condition. All of these conditions can be detected without the use of interrupts by polling various registers and memory locations inside the DD-42900. Even if the IRQ output signals are not connected to the host processor, the IRQ registers can still be useful to the system programmer; the DD-42900 can be set up so the IRQ serves as a single location for the host to poll to determine if any significant events have occurred instead of polling several different registers. This can speed up polling routines. The IRQ outputs may also be useful when made available as a test point for system debugging. An IRQ output set for pulse mode may be used to detect error conditions or to trigger a logic analyzer or oscilloscope to a particular ARINC-429 message or group of messages.

A. The short answer is that there is absolutely no difference in the actual timing of the device. The DD-42900 Users Manual provides two sets of timing information, synchronous and asynchronous. These two sets of timing information describe the timing of the DD-42900 in two different ways. The synchronous timing information describes the read and write cycles relative to the DD-42900 clock. If the processor is running from the same clock as the DD-42900, or a derivative of this clock, then these timing diagrams and tables will provide the system designer with the shortest read and write cycle possibilities. The asynchronous timing information describes the read and write cycles of the DD-42900 without any reference to the DD-42900 clock. If your processor is using a different clock than the DD-42900 the asynchronous timing diagrams and tables provide the timing information needed to guarantee proper operation. Because the DD-42900 is a synchronous device, the read and write cycle times on the asynchronous timing diagrams may appear slightly longer. This is to ensure that set up and hold times are met for various input signals relative to the DD-42900 clock. The system designer is free to choose which set of timing information is most useful for their application.

A. Yes. It is important to note that write cycles do not require the DTACK* or READY handshake signals at all because both the data and address information from the processor are latched internally to the DD-42900 upon the rising edge of the write signal, even if the DD-42900 is not immediately ready to write the data to its final destination. It is also important to note that DTACK* and READY are only required on read cycles from Data Store RAM or Data Match RAM. These are denoted as Type 3 Reads on the DD-42900 data sheet and may take several clock cycles longer than a Type 1 or 2 read. This is because the RAM is shared between the host processor and the internal DD-42900 processors.

There are two ways that the DD-42900 can operate properly without the DTACK* or READY handshake signals. First, if your processor read cycle is long enough to guarantee that a DTACK* would occur before the data from the DD-42900 is sampled for a Type 3 Read Cycle then use of the DTACK* or READY handshake is not necessary. Check the timing data in the DD-42900 data sheet for the maximum time to valid data for a Type 3 Read Cycle.

Second, the DD-42900 can be used in ZERO WAIT mode which provides the system designer with a method to avoid using DTACK* or READY signals to read data from the DD-42900. To use the zero wait mode the ZERO WAIT pin on the DD-42900 must be grounded. In this mode, the software designer must program a dummy read at the address where a read is to be performed. The data obtained from this dummy read should be discarded by the software. The DD-42900 internally fetches the data after the dummy read cycle to an internal data latch. The internal data latch will hold the entire 16- or 32-bit value requested. Subsequent reads to the same address or addresses within the same 16- or 32-bit word can be read as Type 2 reads which require a minimum number of clock cycles for proper access. See the DD-42900 data sheet for the timing requirements of Type 1, Type 2 and Type 3 read cycles.

A. Most ARINC-429 avionic subsystems only require the data from a few addresses. It is in these cases that the DD-42900 works hardest for the system designer by providing the functionality needed by sorting and storing only the data that the system needs and ignoring all the rest. If, however, a system requires all or most of the data to be received, this can be accomplished by using the wild card features in the Data Match Table. The Data Match Table architecture provides a lot of functionality that may not be obvious to the system designer. For example, if a system designer wished to receive data from most addresses, but not all, the designer can program those addresses NOT desired first in the Data Match Table and then place a wild card in the Data Match Table. Since the DD-42900 scans the Data Match Table from the beginning for each word received, the data not desired will be stored in locations which can be ignored by the system. The location corresponding to the wild card location, or Receive FIFO, will contain all data received except those not desired.