ACE and Mini-ACE™: Where Are They Used?

Q. Could you please supply me with a specific aerospace industry use for the Mini-ACE™ product?

A. Our MIL-STD-1553 terminals are used in a wide variety of avionics applications. These include mission computers, flight control computers, displays, transducers, data storage systems, memory loader/verifiers, stores management systems, and missiles. Our 1553 terminals are also used in space applications, including satellites, launch vehicles, space vehicles, and the International Space Station. MIL-STD-1553 is also used on tanks and other ground vehicles.

ACE vs. Mini-ACE™/Mini-ACE™ Plus

Q. What are the differences in pinout and features of the ACE vs. the Mini-ACE™ and Mini-ACE™ Plus?


  1. The ACE includes a TAG_CLK Input signal. There is no TAG_CLK input on the standard Mini-ACE™™. We have found that most ACE users do not require this input signal. Without using TAG_CLK, you have software programmable options of 2, 4, 8, 16, 32, and 64 µs/LSB, with 64 µs/LSB being the most commonly used time tag resolution. Use of the TAG_CLK input (for the original ACE) allows for other resolutions; for example, 10 or 20 µs/LSB.

  2. The Mini-ACE™ does not include a MEMENA-OUT* output signal. This feature is not required for the Mini-ACE™ buffered mode. If you design for transparent mode, the signal MEMENA-OUT* (low) may be derived by gating IOEN* (low)ORDTACK* (low).

  3. The Mini-ACE™ (Plus) does not bring out the INCMD* output signal.

  4. For Mini-ACE™ (Plus), the register bit EXPANDED CROSSING ENABLED (bit 11 of Configuration Register #6) is obsolete. That is, expanded zero crossing, in which the 1553 Manchester decoders sample using both edges of the clock input (CLK_IN) is always enabled. As a result, the Mini-ACE™’s duty cycle tolerance for CLK_IN is tightened from 33% to 67%, to 40% to 60%.

Q. Are there any features that the BU-61688 Mini-ACE™ has that the BU-61586 ACE does not have?

A. Yes.

  1. For Mini-ACE™, the TX_INH_A and TX_INH_B input signals are pinned out. For the ACE, these signals are generally not brought out, except for the BU-61586X6(5 volt) versions.

  2. The BU-61688 (Mini-ACE™ Plus) has 64K X 16 of internal shared RAM, in comparison to the BU-61586 (ACE), which has 12K X 16 RAM.

  3. The BU-61688 Mini-ACE™, like the BU-61586 ACE, allows the use of 16 MHz or 12 MHz clock inputs. However, if your board has a 10 MHz or 20 MHz clock available, the BU-61689 version of the Mini-ACE™™ Plus can use either of these.

  4. In the BU-61688’s (Mini-ACE™ Plus) BC mode, register #0B, the BC FRAME TIME REMAINING REGISTER, will return the actual frame time remaining. For the BU-61586 ACE, this register will return a value of zero.

Q. Are the BU-61585 ACE and the BU-61689 Mini-ACE™ Plus pin compatible? Are there other differences?

  1. They are not pin compatible. The BU-61585 is in a 1.0 X 1.9 inch package. The BU-61689 is in a 1.0 X 1.0 inch package.

  2. The BU-61585 runs off either a 12 MHZ or 16 MHZ clock, while the BU-61689 runs off a 10 MHZ or 20 MHZ clock. The BU-61688 is identical to the BU-61689, but runs off a 12 MHZ or 16 MHZ.

  3. BU-61585 has 12K X 16 of RAM (or, alternatively, can be configured to have 8K X 17), while the BU-61689 (or BU-61688) has 64K X 16 of RAM.

Q.  Have both the ACE and Mini-ACE™ passed MIL-STD-1553 RT validation testing?

A. Yes. The Mini-ACE™ hybrid, which incorporates a 5V (only) transceiver (there are no 15V or 12V versions of the Mini-ACE™) has passed the MIL-STD-1553 RT Validation Test Plan (VTP). This test comprehensively exercises both the transceiver and protocol (logic) portions of the Mini-ACE™ hybrids. The Mini-ACE™ passed the RT VTP at all three temperatures (-55, +25, and +125 degrees C). We have a test report available. If you would like a copy, we can supply it.

In addition, Appendix E of our ACE User’s Guide is a report of the BU-61580D2-110 ACE passing the RT VTP. The RT protocol chip used in the Mini-ACE™ and Mini-ACE™ plus (BU-61688/89) hybrids includes the same RT protocol functionality as the protocol chip used in the original BU-61580 ACE hybrid.

Mini-ACE™ vs. Mini-ACE™ Plus

Q. What are the pin compatibility issues between Mini-ACE™ and Mini-ACE™ Plus?

A. For the Mini-ACE™ (BU-65178/61588), the upper four address lines (A15-A12)are not used. However, use of the 4K RAM (Mini-ACE™) version with the 4 address lines connected to A15-A12 provides a compatibility path to the BU-61688/89 Mini-ACE™ Plus with its 64K of RAM. For the BU-65179 Mini-ACE™ RT with auto-boot, these signals take on different functions, and should not be connected to A15-A12.

ACE and Mini-ACE™: General

Q. What is the purpose of the ACE’s TX_INH (Transmit Inhibit) input signals?

A. These provide a hardware mechanism for shutting down a faulty 1553 transmitter. In addition, these signals may be used to ensure that a Mini-ACE™ (Plus) cannot transmit when configured for monitor mode. Also, the TX_INH inputs provide compliance to the EFA/STANAG-3910 spec.

Q. I have a question concerning the Mini-ACE™’s TX_INH_A and TX_INH_B signals. Do these need an external pull down if not used?

A. For normal operation (i.e., assuming that you want to use, rather than shut off, the 1553 transmitters), the TX_INH_A and TX_INH_B inputs should be hardwired to logic "0" (ground).

Make a direct connection to ground, rather than through a pull-down resistor. A pull-down-resistor (e.g., 10K ohms) will not provide a reliable logic "0" connection, due to leakage current (the max leakage IILis about 400 µA).

Q. The way we’ve always configured the ACE and Mini-ACE™ is for the 16-bit Buffered Mode. Is it correct to say that they use DMA?

A. Sort of. The memory configuration of the ACE/Mini-ACE™’s buffered mode is referred to as “shared RAM”, rather than DMA. However, in operation, the shared RAM interface uses a DMA-type mechanism in that there are data transfers between the Mini-ACE™’s protocol logic (encoder/decoder and memory management logic) and the internal shared RAM, that take placenotunder CPU control.
That is, these transfers take place autonomously, independent of the host CPU. Since the host processor may also access this internal shared RAM, the Mini-ACE™ includes internal arbitration logic. This logic acts as a “traffic cop”, to enable – at any point in time, for either the host processor or the Mini-ACE™’s internal logic –but not both simultaneously– to be able access the shared RAM.

Q. What is the ACE/Mini-ACE™’s radiation tolerance?

A. In 1995, we had radiation testing performed on a BU-61581 ACE (with 1.25 micron J’ protocol chip and 15V transceiver). Quoting from the report of this testing: at 2.8K rads, 5K rads, and 10K rads; and, for neutron fluences of 1.20•1012 and 2.80•1012, "The devices encountered no failures at this level". There were no single event effects exhibited at proton fluences of 1.0•1010protons/cm2.

Q. We are using the BU-61580 as a 1553 bus controller. We are only using bus A and not bus B. Do we need to terminate bus B on pins 34 and 35, and if so, what is the easiest way of doing it? We don't want to use the 1.4:1 transformer if not necessary, because of the extra cost.

A. As long as you're not using bus B, there's no need for a coupling transformer or termination resistors.

Q. Are there any special grounding considerations for the Mini-ACE™?

A. In the original ACE, the analog (transceiver) and digital grounds are not connected together inside the hybrid. In the Mini-ACE™, as a means of reducing the effects of ground bounce, these grounds are connected together inside the hybrid.
Basically however, the same rules apply: when transmitting, the large ground currents flow through the transformer (primary) center tap, not through the hybrid ground pins. Therefore, you still need to:

  1. Connect all three Mini-ACE™ ground pins directly to the (digital) ground plane.

  2. Have a heavy ground trace going to the transformer center tap connections.

  3. This trace (to the transformer center taps) should either connect through a low-impedance path back to the +5V power supply return. Alternatively, you can connect this trace directly to the board's ground plane, assuming that the ground plane serves as both analog and digital ground (and return paths).

  4. Of course, the ground and supply planes should NOT extend directly under the transformers or the analog signal traces. The added capacitance could make the terminal’s input impedance fall below the 1553B stub-coupled minimum of 1000 ohms.

Q. For the BU-61588 Mini-ACE™, please clarify the note regarding decoupling capacitors. Are one 10 µf and one 0.1 µf recommended for each of the two Vcc pins for a total of two 10 µf and two 0.1 µf?

A. For the BU-61588, it is recommended to put individual 10 µf and 0.1 µf capacitors near each of the two transceiver power pins (20 and 72). Pin 72 is the +5V power input to the Channel A transceiver, while pin 20 is the +5V power input to the Channel B transceiver.
To minimize the trace lengths (and therefore parasitic inductance) to each of these power inputs, it is best to provide separate decoupling for each.

Q. For the BU-65179, how is the clock frequency specified? Also, how does the RT AUTO-BOOT function work?

A. For the BU-65179, CLK_SEL1 and CLK_SEL_0 are used to designate the frequency of the CLK_IN input as follows:
CLK_SEL_1 CLK_SEL_0 Clock Frequency
0 0 10 MHz
0 1 20 MHz
1 0 12 MHz
1 1 16 MHz
As for the RT_BOOT_L signal: if it is connected to logic "1", the BU-65179 initializes in "Idle" mode. In this case, it is necessary for the host processor to write values of logic "1" and logic "0" to bits 15 and 14 respectively of Configuration Register #1 to put the BU-65179 online as a functioning (responding) RT. In addition, all of the RT status word bits will be either set or cleared as the result of writing to Configuration Register #1.
If RT_BOOT_L is connected to logic "0", the BU-65179 will initialize as a functioning RT without having to write to Configuration Register #1. In addition, the RT status word "Busy" bit will initialize as set, while all of the other RT status word bits will initialize as cleared. That is, the BU-65179 RT will respond with its "Busy" bit set immediately following power turn-on.

ACE and Mini-ACE™: BC mode

Q. For Mini-ACE™/Mini-ACE™ Plus and Enhanced Mini-ACE™ BC, how does intermessage gap timing work?

A. For Mini-ACE™ (Plus) and Enhanced Mini-ACE™, the BC provides a "time-to-next-message" parameter (rather than true "intermessage gap time") for each BC message. The “time to next message” parameter defines the time from the start of the current message to the time of the start of the subsequent message.
In addition, the BC architecture of the Enhanced Mini-ACE™ enables you to implement a true "intermessage gap time" function by means of the DLY (delay) instruction. The delay time is programmable in 1 µs steps, up to 65.535 ms. The overall intermessage gap time will then be approximately 10 µs plus the value of the DLY parameter.

Q. For the Mini-ACE™ BC, when will the BC END_OF_FRAME interrupt occur?

A. The BC END_OF_FRAME interrupt is issued at the completion of the last message of the frame, regardless of whether or not the Intermessage Gap Time (time-to-next-message) timer and/or the BC frame timer have timed out.

Q. For the ACE BC mode, is the time tag word written at the start of a message, the end of a message, or both?

A. The Time Tag word is written to the BC descriptor stack during the start-of-message sequence and again during the end-of-message sequence.

Q. What must the RT address input be when the device is used only as a BC?

A. For BC operation, it doesn't matter. However, if you plan on running the ACE self-test vectors, you must connect the RT address inputs RTAD4-RTAD0 to a valid RT address (0 to 30) with correct parity (i.e., odd parity for RTADP) in order for the self-test vectors to pass.

Q. Are there any pull-ups required on the Mini-ACE™ RT address signals?

A. The Mini-ACE™’s RT address signals include internal pull-ups. Actually, these are current sources (from +5V), with the current values between approximately 50 and 400 µA. For best noise immunity, the RT address inputs should be connected directly to either +5V or LOGIC GROUND. In particular, pulldown resistors should not be used.

Q. Am I correct in assuming that the BC command stack (in ENHANCED mode) rolls over at multiples of 4*(Selected Command Stack Size)?

A. No. The size of the BC/RT command stack is programmable by means of bits 14 and 13 of Configuration Register #3. The four choices are:

Bit 14 Bit 13 Stack Size
0 0 256 words (64 messages)
0 1 512 words (128 messages)
1 0 1024 words (256 messages)
1 1 2048 words (512 messages)

Therefore (for example), if bits 14 and 13 are both "0", the stack will roll over every 256 words, or 64 messages. The stack will roll over at an address equal to modulo the programmed stack size (e.g., 256, 512, ...).

Q. Does the Mini-ACE™ have a combined BC/Monitor mode?

A. No. The ACE and Mini-ACE™ do not include an explicit BC-MT mode. However, with the Mini-ACE™ bus controller mode, you essentially get a monitor for "free". That is, in the ACE's BC message block, all of the words of a message are stored: that is, the BC's Command Word, the RT's Status Word (including both status words for an RT-to-RT transfer), and any and all Data Words transmitted by the BC or the RT. In addition, the Mini-ACE™ will flag any error conditions: either failure of its own loopback test, and/or any no responses or errors in responses from RTs. So, in essence, you're getting all the functions of a bus monitor with the ACE's BC mode. Also, the Mini-ACE™ does include a combined RT/Monitor mode. In this mode, the ACE operates as a full-function RT for one RT address, and a selective message monitor for all other RT addresses.

Q. We are using two Mini-ACE™s on two separate processor cards separated by a VME bus connection. We are trying to synchronize these two devices such that they send out minor frames or a Synchronize without data mode code message on two separate buses within a guaranteed 100 µsof each other. What mechanisms do you suggest for allowing us to do this?

A. For synchronizing between two Mini-ACE™s, the external trigger is probably a good mechanism to use. To use the external trigger feature, you need to program bits 8, 7, and 6 of Configuration Register #1 as follows:
Bit 8 (FRAME AUTO-REPEAT): logic "1"

This will configure the Mini-ACE™ for a "single frame", such that each frame may be initiated by a rising edge to the EXT_TRIG input signal, or by a software start command. The EXT_TRIG signals may be connected together, to a circuit generating this rising edge. By so doing, the Synchronize mode commands from the two Mini-ACE™s will be very tightly synchronized.

Alternatively, you could use the software start mechanism; i.e., writing a value of 02h to the Start/Reset Register to each of the two Mini-ACE™s. As long as you perform these two write cycles within a few microseconds, the start of transmission for the two Synchronize (without data) mode commands will be tightly synchronized.

ACE and Mini-ACE™: RT Mode

Q. For the BU-65178, what means are there for specifying RT address?

A. There are three methods:

  1. Hardwire RT_AD_LAT to logic "1". In this configuration, the BU-65178's RT address will be programmable by means of Configuration Register #5. Note that when you write Configuration Register #5, the RT address will be latched from the RTAD4-RTAD0 and RTADP pins, and not from the processor address bus (D15-D0). However, if you connect RTAD4 to D5 .... RTAD0 to D1, and RTADP to D0, you will allow the RT address to be software programmable.

  2. Hardwire RT_AD_LAT to logic "0". This will configure the RT address to be hardwired, by means of RTAD4-RTAD0 and RTADP.

  3. Include a circuit to provide a low-to-high transition on the RT_AD_LAT input pin (some time after MSTCLR* has settled to logic "1"). This will cause the values presented on RTAD-4-RTAD0 and RTADP to be latched internally on this rising edge.

Q. What is the function of the BU-65178 Mini-ACE™’s SSFLAG*/EXT_TRIG input?

A. For the BU-65178 RT Mini-ACE™, the only function of the SSFLAG*/EXT_TRIG input signal is as a SSFLAG* (Subsystem Flag) input. The "EXT_TRIG" function is not applicable to the BU-65178 RT. EXT_TRIG is a BC and Monitor function that is only applicable to the BU-61588 Mini-ACE™ BC/RT/MT, and the BU-61688/89 Mini-ACE™ Plus BC/RT/MT.

If SSFLAG* is connected to logic "0", this will cause the Subsystem Flag bit in the RT Status word to be set to logic "1". If SSFLAG* is connected to logic "1", the value of Subsystem Flag will be determined by the software programming of Configuration Register #1. Therefore, if you don't intend to use this function, I recommend that you hardwire SSFLAG*/EXT_TRIG to logic "1".

One use of the SSFLAG* input is to provide a hardware mechanism for a processor watchdog timer to be able to signal to the 1553 RT that it has timed out (i.e., that the processor has hung up).

Q.  We have connected the Mini-ACE™’s SSFLAG* input pin to a processor
watchdog timer circuit. Whenever the host fails to retrigger the watchdog timer, the SSFLAG* pin is latched low in order to indicate a sub-system malfunction/failure. We are looking to run a power-up built-in test on the watchdog circuit, such that when we allow this timer to timeout we can read the RT Status Word (Register 0E) and verify that the SSFLAG* bit is indeed set.

The problem is that the SSFLAG* pin is sampled and the Status Word is updated only during a Start-of-Message (SOM) sequence. An SOM can occur only when the RT receives a command from the external Bus Controller. At the time when we want to run this test, we cannot tell whether the Bus Controller is up and running. The test may therefore fail either due to a watchdog failure or a delayed BC start-up.

The question is: is there a way to cause the RT to sample the SSFLAG* input pin and update the Status Word without waiting for an SOM to occur? That is, is it possible to trigger a SOM from the host side?

A. Yes.There is a way of causing the RT Status Register to update. It involves use of the Enhanced Mini-ACE™'s test mode. Here's what you need to do:

  1. Cause the watchdog timer to timeout, which will cause the Enhanced Mini-ACE™'s SSFLAG* input signal to be logic "0".

  2. Read the RT Status Word Register (register address 0E). If SUBSYSTEM FLAG, bit 2 of this register, returns logic "1", then you can skip the following steps. If this bit is logic "0", then you need to perform steps (3) through (7).

  3. Make sure that the Enhanced Mini-ACE™ is programmed for RT mode, and that ENHANCED MODE is enabled; i.e., bit 15 of Configuration Register 3 is logic "1".

  4. Read, and then re-write, Configuration Register #4, setting the value of the three lower bits to 111 (binary). This will put the Enhanced Mini-ACE™ in GENERAL TEST MODE.

  5. Write a value of 2000 (hex) to Test Mode Register 3 (register address 13 (hex)). This will cause the RT Status Word Register to update (as if a message has been received from the BC).

  6. Read, and then re-write, Configuration Register #4, this time setting the value of the three lower bits to 000 (binary). This will put the Enhanced Mini-ACE™ back into its normal RT mode of operation.

  7. Once again, read the RT Status Word Register (register address 0E). If SUBSYSTEM FLAG, bit 2 of this register, returns a value of logic "1", then the test has passed.

Q. For Mini-ACE™, I understand the hardware setting of RT Address. One design we saw had a “software settable option”, by writing to a register. My assumption is that this must use an external register outside the ACE, is that correct?

A. The Mini-ACE™’s software programmable RT address does not require an external register. For the BU-65178/79 or BU-61588 Mini-ACE™ or the BU-616688/689 Mini-ACE™ Plus, the steps to use the software programmable RT address feature are as follows (the first two steps are hardware design; the last four steps are software programming):

  1. Connect the signal RT_AD_LAT to logic “1”.

  2. Connect RTAD4 to data bus D5, RTAD3 to D4, …, RTAD0 to D1, and RTADP to D0.

  3. Program the ACE for ENHANCED MODE, by setting bit 15 of Configuration Register #3 to logic “1”.

  4. Enable the RT address to be software programmed by setting LATCH RT ADDRESS WITH CONFIGURATION REGISTER #5 (bit 3 of Configuration Register #4) to logic “1”.

  5. Program the RT address by writing to Configuration Register #5, using the bit mapping defined in step (2).

  6. To prevent the software from inadvertently changing the RT address, clear LATCH RT ADDRESS WITH CONFIGURATION REGISTER #5 (bit 3 of Configuration Register #4) to logic “0”.

Q. If the host sets the SERVICE REQUEST* bit in Configuration Register #1 to logic “0”, and the “Clear Service Request” feature is used, is it possible for the BC to not see the Service Request bit set to logic “1” in the RT Status Word?

A. Yes. If the host sets SERVICE REQUEST* to logic "0" between the SOM and EOM sequences for a Transmit vector word mode code message, the ACE RT will respond with the Service Request status bit equal to "0", and the SERVICE REQUEST* register bit will automatically clear to logic "1". Therefore, the BC will never see the Service request bit set to logic "1". The rationale for this is that the BC should only send a Transmit vector word mode command after it has detected a Service request bit of logic "1" in a previous message.

Q. When the time tag is loaded on a Synchronize with data mode command, and the time tag resolution is 64 µs/LSB, does the counter wait 64 µs before it increments? That is, is the resolution countdown cleared when the time tag value is loaded, or is it free running?

A. The Time Tag counter is loaded immediately (i.e., asynchronously) following receipt of the data word for a Synchronize (with data) mode code. In addition, the 64 µs clock circuit is reset to zero at this time. That is, the time tag counter won't increment an LSB until a full 64 µs has elapsed.

Q. If ENHANCED MODE CODE HANDLING is enabled, for a receive mode command, will the data word be stored in the third word of the message descriptor in the RT stack and/or the individual fixed location in shared RAM? On a transmit mode command, where will the Mini-ACE™ read data from?

A. For a receive mode command with data, the data word will be stored in both places: the third word of the message descriptor and the enhanced mode code data table. For mode commands without data, the third word of the descriptor will not be written to. For a transmit mode code command, the data will be read from the enhanced mode code data table and written to the third word of the descriptor.

Q. I have a question about the RT subaddress double buffering mode. For broadcast receive subaddress 19 programmed for double buffered mode, the first transmission from the bus controller goes to 0x4A0, as it should because this is block 0 of the buffer. The second set of data should go to 0x4C0 -- block 1 of the buffer, but it does not. The data ends up at 0x480. This is 32 words below the base address of the buffer, rather than 32 words above the base address of the buffer.

If I move the base of the buffer to 0x4C0, the double buffering works fine. The first transmission from the BC goes to 0x4C0 and the second transmission goes to 0x4E0. It also works normally if I change the base of the buffer to 0x540. But, if I move the base of the buffer to 0x5A0 the problem occurs again. The first transmission goes to 0x5A0 and the second transmission goes to 0x580 when it should go to 0x5C0.

A. The way the subaddress double buffering works is that after a valid message is received to a receive(/broadcast) or broadcast subaddress with double buffering enabled, then bit 5 of the lookup table pointer will betoggled.

That is, the updated lookup table pointer value = (old lookup table pointer value XOR 32), and not (old lookup table pointer + 32).

In other words, if the pointer's value is initially XXXX XXXX XX00 0000, it becomes XXXX XXXX XX10 0000. Similarly, if it's value is XXXX XXXX XX10 0000, it "ping-pongs" to a value of XXXX XXXX XX00 0000.

Q. We are using a Single Board Computer VME card with a BU-61580 ACE. What happens when a Bus Controller (also using a BU-61580) tries to communicate with a BU-61580 whose RT address is correct, but the parity is incorrect?

A. A BU-61580 RT configured with an incorrect RT Address parity bit will not receive or respond to commands to its own RT address. Note however that the BU-61580 will still be able to receive commands and data sent to the broadcast address (address 31).

Monitor Mode

Q. For using the Mini-ACE™ in Monitor mode, can I use the two RAM areas A and B to organize double buffering?

A. Yes. That way, you can "ping-pong" between the two areas. While one is storing
1553 monitored data, the second one can be read out by the host.

Q. Current area (A or B) command or data stack overflow causes the stack pointer to wrap to the beginning of the same stack, so that in the case of the data stack this causes corruption of the oldest message. Correct?

A. Yes, the command and/or data stack pointer(s) will roll over to the top of the stack. As you point out, this can cause message corruption. What I suggest to avoid such a problem is that when your host processor initializes the stack pointer, to position it a ways down from the top.

In the case of the monitor data stack, I would allow for 35 words at the top of the stack, to accommodate the maximum size message to be received; i.e., an RT-to-RT transfer, with the second command word + 32 data words + 2 status words. Similarly, for the monitor command stack, I would suggest initializing the stack pointer such that there are four locations -- the size of one message descriptor -- free at the top of the stack.

For the BU-61588 (4K internal RAM), what I would suggest is to use a monitor command stack size of 256 words for each of area A and area B. Likewise, for the monitor data stack, I would use a stack size of 1024 words for each of the two data stacks.

For the case of the Enhanced Mini-ACE™, the 50% rollover interrupt feature should be used. That is, the monitor may be programmed to issue interrupt requests when the monitor data stack and/or the monitor command (descriptor) stack is either half-full or 100% full. In this way, the host can read data from the most recently filled half data stack or half descriptor stack, while the monitor continues to store new data received from the 1553 bus in the other half stack.

Q. When will the corresponding interrupt (rollover) occur? The stack pointer rollover event is not reflected in the MT SOM or EOM sequence.

A. For the command stack, the command stack rollover interrupt occurs at the beginning of a received message. For the monitor data stack rollover, the interrupt occurs at the end of the message that resulted in the rollover. In either case, the event will be reflected in the Interrupt Status Register (assuming that interrupts are enabled for these events).

Q. Let's suppose, for example, that Monitor Command Stack Pointer A (0x0102) is given an initial value of 0x0600 and the Monitor Command (descriptor) Stack size is 256 bytes. I thought that the command data is then written into addresses 0x0600 through 0x0500 and the next byte of command data will be written once more into 0x0600 address, isn't it? If I initialize Pointer A to 0x05FC, will it roll over to the 0x05FC address?

A. If you initialize for a Command Stack size of 256, and initialize the Command Stack Pointer A (location 0x0102) to a value of 0x0600, it will increment by four (4) at the start of each received (monitored) message. That is, it will increment to 0x0604, 0x0608, .... 0x06F8, 0x06FC, before rolling back to 0x0600.

By so doing, note that the 4-word descriptor for the first monitored message received and stored will be stored in locations 0x0600-0x0603. The descriptor for the second received message will go in 0x0604-0x0607, ..... the descriptor for the 64th message will go in 0x06FC-0x06FF and, if enabled, a Monitor Command Stack Rollover interrupt will be generated at the start of that (the 64th) message. The descriptor for the 65th message will then overwrite that for the first message, in locations 0x0600-0x0603.

Q. Suppose I do the following: Initialize stack to 0x600, for example, and interrupt on stack rollover. This interrupt will be of highest priority and the first that I will do will be area switching. According to my calculations, I have at least 27 µs for area switching, which is more than enough for me.

A. That should work OK. I just suggest that during your interrupt service routine that you initialize the (A or B) Command Stack pointer to 0x0604, rather than 0x0600. The reason is that 27 µs could be marginal, for the case where the message which caused the command stack rollover is a broadcast mode code with no data words. In this case, if the intermessage gap time is 4 µs (per –1553B), there could theoretically be a gap time between the start of successive messages of about 22 µs. By initializing to 0x0604 rather than 0x0600, the message descriptor stored at 0x0600-0x0603 will not be overwritten.

Q. Can I reinitialize the Command (or Data) stack pointer "on the fly"? And if yes, when is this new value taken in to consideration by firmware?

A. You may reinitialize (write to) the Command Stack Pointer locationat any time. The Mini-ACE™ includes an arbitration circuit, to prevent "crashes" between memory accesses by the internal logic circuitry and by your host processor.

Keep in mind, the digital portion of the BU-61588 does not include any internal processor or "firmware". It's a state machine logic circuit.

Remember, the Monitor Command Stack pointer is both sampled - to determine the starting location for the current message's 4-word descriptor –and incremented by four, and re-written during the monitor start-of-message (SOM) transfer sequence.

The Mini-ACE™ arbitration logic prevents you from writing to memory (e.g., the Monitor Command Stack Pointer) during the monitor SOM transfer sequence. Therefore, if you write to the stack pointer before the SOM sequence, then the value will be used for the next message that comes in. However, if you write to the Command Stack Pointer after the SOM sequence for a message has occurred, then that (current) message will store its descriptor information (Block Status Word, Time Tag, etc.) at the old (previous) location; that is, the one that was accessed during the message's SOM sequence.

If you initialize the Command Stack Pointer to 0x0604, then the 64th message, which will result in a Command Stack Rollover Interrupt (if enabled) at the start of the message, will result in the descriptor for the 64th (next) message to be stored in 0x0600-0x0603. Therefore, if your interrupt service routine does not react fast enough, the 64th message will not overwrite a descriptor in 0x0600-0x0603, since there was no message stored there previously.

Q. For the Mini-ACE™’s selective monitor mode, when do the Monitor Command Stack and Data Stack rollovers occur?

A. The way that the Monitor Command Stack and Data Stack operate is that they always roll over at an address boundary of modulo the programmed stack size, regardless of the values that the pointers were initialized to.

Q. It appears that the Mini-ACE™ Message Monitor ignores a “No Response” error condition when there is a data word with parity error in the message. Is this correct?

A. The ACE monitor stops monitoring once an error (for example, a parity error) is detected in a message. Therefore, the monitor will not detect a subsequent response timeout condition in the same message. In fact, if there is a response to a message with an error (e.g., parity), the monitor will interpret the status word as the command word for a new message.

ACE and Mini-ACE™: Interrupts

Q. Will the Interrupt Status Register’s MASTER INTERRUPT bit be set for an event/condition that is masked “disabled”?

A. No. MASTER INTERRUPT will only occur for an event/condition that is enabled by means of the Interrupt Mask Register.

ACE and Mini-ACE™: Troubleshooting

Q. My BU-61580 RT doesn’t respond to command from the bus controller. What should I look at?

A. Here are a few things that you can look at:

  1. You need to make sure that RDAD4 through RTAD0 are connected to +5V or GROUND for the correct desired RT address and that the RT address parity signal, RTADP, is connected to +5V or GND, in order to ensure a correct odd parity sum. That is, the number of logic "1"s for RTAD4-RTAD0 AND RTADP must be an odd number. For example, if your desired RT Address is 0, then RTADP must be connected to logic "1". If the RT address parity is incorrect, the BU-61580 RT will not recognize any messages that the BC sends to its RT address.

  2. You need to provide a properly terminated 1553 bus (that is, 70 to 85 ohms at each end of the bus). An unterminated bus may result in transmission line reflections, resulting in waveform distortions. In such a case, the RT may not recognize an otherwise valid message from the bus controller.

  3. Make sure that you have a clean 16 MHZ clock input to CLK_IN. Note that 16 MHZ is the default clock frequency for the BUS-61580. You may also use a 12 MHZ clock for the BU-61580, but this would require you to modify your initialization software by programming for ENHANCED mode and then programming bit 15 of Configuration Register #5 to logic "1".

    In addition, you need to make sure that the clock input has a duty cycle in the range of 40% to 60%, and does not have significant undershoot, overshoot, or transition noise (on the rising and falling edges). If you see any of these type(s) of problems, they are generally layout related: either transmission line type reflections (possibly from long (more than 1 or 2 inches), or "stub" traces) and/or from crosstalk from other signals on your board, usually from other digital signals.

  4. You need to make sure that the center taps of your isolation transformers are grounded on the "primary" side; that is, the side of the transformers connected to the BU-61580. If you don't ground the center taps, you might be able to receive messages from the bus controller, but the BU-61580 RT won't be able to transmit any responses.

Q. We have a custom DSP board with two BU-65170 Mini-ACE™s. On occasion, one of the BU-65170s stops generating interrupts to the DSP following reception of BC-RT messages. I have not been able to pin this event on anything the DSP is doing. I have two questions:

  1. (1) What can cause the interrupts to stop? The Interrupt Mask Register (00h) is not being corrupted and the messages on the 1553 bus are still valid. I believe the BU-65170 is responding with correct status since our monitor is not showing any errors, but I have not verified this by hooking a scope to the bus.
  2. (2)   What is the best way to "jump start" the 65170 when this happens?

A. You say that the Interrupt Mask Register is not getting corrupted. Here are some
things for you to consider:

  1. You should determine whether or not the BU-65170's descriptor stack pointer continues to increment. If it does, this points to an "interrupt-specific" type of error. In this case, you should read the value of the messages' Block Status Words to try to gain insight into the problem.

    If the stack pointer is not incrementing, this points to an error receiving and processing valid messages from the 1553 bus. This could possibly be a bus controller, termination, transformer, or other electrical problem; an inadvertent change in the BU-65170's RT address; a power glitch; an inadvertent hardware reset (MSTCLR* input pulsing low); or a software problem (e.g., inadvertently writing an incorrect value to a register).

  2. What interrupt are you enabling? EOM? Others?

  3. Is the BU-65170's interrupt output (INT*) configured as a pulse or level type signal (bit 3 of Configuration Register #2)? Remember, if it's configured as a level, you won't get a subsequent interrupt until you first clear the INT* output and Interrupt Status Register from the previous interrupt.

  4. Are you using INTERRUPT STATUS AUTO CLEAR (bit 4 of Configuration Register #2)? If you are not, it is necessary to write a value of "1" to bit 2 (INTERRUPT RESET) of the Start/Reset Register in order to clear the Interrupt Status Register and the INT* output (if it’s programmed for “level”). If INT* is programmed to provide a level type of interrupt and is not cleared following the first interrupt request, then the host will not detect subsequent interrupt requests.

  5. Another thing that you might look at: try setting ENHANCED INTERRUPTS, bit 15 of Configuration Register #2 to logic "1" (note that to use this feature, it is first necessary to write a value of logic "1" to ENHANCED MODE, bit 15 of Configuration Register #3). By doing this, it is possible for bits in the Interrupt Status Register to become set, even if the respective events/conditions have been disabled from causing interrupt requests. Therefore, I would suggest to write a value of 0000h the Interrupt Mask Register to disable all interrupts, and then periodically poll the Interrupt Status Register. In this scenario, the ISR bits (e.g., EOM) should still become set. Of course, it will then be necessary to clear the ISR by either AUTO-CLEAR, or by writing a value of 0004h (INTERRUPT RESET) to the Start/Reset Register.

  6. You need to make sure that the values of registers other than the Interrupt Mask Register are not changing. For example, that the upper two bits (15 and 14) of Configuration Register #1 are staying as "1" and "0" respectively (for example, a combination of "0" and "0" will cause the BU-65170 to revert to its "idle" (non-active) mode.

  7. You need to verify that the BU-65170's RT address (and parity) inputs are not changing.

  8. Finally, you need to ensure there isn't a hardware related problem between
    the BU-65170's INT* output and your DSP's interrupt request input, such as logic related to interrupt requests from other hardware circuits.

ACE and Mini-ACE™: Self-Test Issues

Q. How is the Mini-ACE™ put into its general test mode?

A. By setting the MSB (bit 15) of Configuration Register 3 (ENHANCED MODE), and then writing a value of 7 (111) to the three LS bits of configuration register 4.

Q. How are the test vectors interpreted?

A. To illustrate by example:
V W R 0003 0001 means vector write to register 3 the value 0001.
V R R 0000 0040 means vector read (and verify) of register 0 the expected value 0040.
V W M 0000 0655 means vector write to memory location 0 the value 0655.

Q. I downloaded the test vectors from the DDC web page. It turns out that there is a acelib function that loads and executes these vectors. The function is called BuVectorTest(). I've used BuVectorTest() to run the BC/RT/MT vectors (TEST.VEC) on our Radstone PMC1553 card.

There appear to be only a couple of failures, all in the "Interrupt Status Register & Interrupt Mask Tests" section. Could you take a quick look at the failures below?

The first failure is at line 85 of TEST.VEC:
V R R 0013 ECEB

The register address 0013 (hex) appears to be test mode register 3, which isn't documented in the ACE user's guide. The expected data is ECEB, but we get ECFB.

If I comment out line 85 (with the letter 'D' at the beginning of the line), I get a second failure at line 86 of TEST.VEC:
V R R 0006 FFFF

It looks like we want the ISR to be FFFF (it was set to this value at line 84). Instead, we get a value of 0 from the ISR. Should it be
possible to write to the ISR and expect to get back what we wrote to it (in test mode)?

A. The problem that you are seeing has to do with the ACE's host processor responding to an interrupt request, and then reading the ISR (Interrupt Status Register). As a result, the value of the ISR is getting cleared to 0.
Test register 0013h is a reading of the ACE’s internal state. Register 0006 is the ISR.
To prevent this problem from occurring and to enable your ACE to pass self-test, you will need to either:

(1) Have the ACE's host processor disable interrupts during self-test;or

(2) Make sure that the ACE's host processor does NOT read the value of the ACE's ISR during the interrupt service routine while you are in self-test.

Q. Is there any means to exercise, and therefore test the ACE/Mini-ACE™/Enhanced Mini-ACE™/SP’ACE’s transmitter fail safe timer? Verifying the operation of this circuit is required by the RT Validation Test Plan (paragraph

A. To induce a transmitter timeout condition for the ACE/SP'ACE/Mini-ACE™, set the lower three bits (TEST MODE) of Configuration Register #4 to a value of 4 (100). This configures the ACE test mode for "Fail safe timer" test mode. When you do this, the ACE will transmit until a timeout condition occurs for every transmission. That is, for every RT response, or for every BC message transmitted. The value of the failsafe timeout timer is either 668 µs for ACE or SP’ACE, or 660.5 µs for Mini-ACE™ or Enhanced Mini-ACE™.

Q. When we put the Mini-ACE™ into test mode, and issue a test command 0x2000 on Test Mode Register 3 (0x13), do we transmit any data on the bus? Being a Remote Terminal, we are not supposed to transmit anything unless actually commanded by the Bus Controller.

A. When the RT is in TEST MODE, the Enhanced Mini-ACE™ will not transmit any words on the 1553 bus.